1. Field of the Invention
The present invention relates to semiconductor integrated circuits and, more particularly, to test circuits built into the integrated circuits that enable efficient testing of embedded memory, especially read/write memory.
2. Description of the Related Art
As integrated circuits achieve higher and higher levels of integration it is common to find several memory blocks of differing sizes embedded within blocks of logic in the integrated circuit. A typical example of embedded memory is the data and instruction cache memories along with their associated tag and valid data cache memories that are embedded in most modem microprocessors. These memories are called xe2x80x9cembeddedxe2x80x9d because they are not directly accessible from the input and output pins of the integrated circuit chip. Instead, an embedded memory is separated by logic blocks from the input and output pins in ordinary operation of the circuit. Testing of these embedded memories is therefore complicated because any access to these memories during normal operation of the chip is mediated by the associated logic. Integrated circuits are widely used because they offer a high functionality per unit of cost. To achieve the economies necessary in modern integrated circuit manufacturing, it is necessary to minimize both the cost of the raw circuit as well as the cost of testing it. In many cases, the cost of testing the device is comparable to the cost of manufacturing the raw die in the fabrication plant. The cost of a functional die is roughly proportional to the inverse exponential of the die area. Therefore, it is necessary to minimize the die area in order to minimize die costs. The cost of testing is approximately proportional to the product of the test time and the cost of the testing equipment. Therefore, it is desirable to minimize both the test time and the complexity of the test equipment to minimize testing costs. Testing of memories is generally accomplished by applying test vectors to the memory and reading back the results to ensure proper memory operation.
One possible approach to testing embedded memories is to connect the control, address, and data lines of the memories to external pads of the integrated circuit. Multiplexer blocks are implemented within the integrated circuit to connect the embedded memories either to the external pads for testing or to internal buses for standard circuit operation. A drawback to this approach is that the extra bus lines and pads increase the size of the semiconductor die and the extra pads increase the number of pins required of the tester. The cost of the tester is generally roughly proportional to the number of pins. Since the trend is toward wide memories of increasingly large capacity in modern ICs, the number of extra buses and pads required can frequently exceed one-hundred, which represents a prohibitive cost burden. To avoid excessive costs while simultaneously providing adequate fault coverage, there has been a movement toward built-in self test (BIST) of integrated circuits. This approach relies on circuitry built into the integrated circuit to test the memories and report the results to off-chip electronics by means of a restricted number of pins. An example of BIST methodology are the commonly-used JTAG standards. Special test modes which disable the normal operation of the circuit are invoked to enable BIST. BIST attempts to provide complete fault coverage while minimizing test time and the area of the die that is occupied by the BIST circuitry. In some applications, it is also desirable that diagnostic information be available for faults that are detected. These requirements are in conflict, so various schemes have been developed which optimize one factor at the expense of the others.
One disadvantage of conventional BIST engines (e.g., macros), is the time necessary to test a memory array. For example, as disclosed in U.S. Pat. No. 5,568,437 to Jamal (hereinafter xe2x80x9cJamalxe2x80x9d), incorporated herein by reference, a conventional BIST method and system are disclosed wherein the BIST engine stores and attempts to retrieve data from a memory array. If the data retrieved from the memory array does not match the data stored therein, the array contains one or more defects. The conventional BIST macro in Jamal determines which memory elements of the memory array are defective by stopping the BIST engine when an erroneous retrieval from the array is sensed. The address of the memory element is stored in a defect scan register and the BIST engine is reinitialized and the array testing is restarted from the previously located defective memory element until the next defective memory element is located. All addresses of the remaining defective memory elements are also added to the defect scan register. Once the BIST determines that no more defective memory elements are present, it outputs the addresses of the defective memory elements.
Therefore, with the conventional BIST macros, such as the one disclosed in Jamal, the BIST engine must be repeatedly reinitialized and the entire array is rechecked until all defective memory elements are located. This is a very time- consuming operation and takes on the order of minutes to test each chip. To the contrary, the invention described below provides a system where the BIST engine does not need to be restarted at each defective memory element. This reduces the time necessary to test an array to an order of milli-seconds per chip for single cell faults and seconds per chip for complete array wipe outs.
In addition, many faults occuring in today""s technologies occur at speed. In Jamal""s invention a real-time fail pin is used to monitor which tester cycle failed so a table of failing address""s can be built to re-run the array BIST machine to each failing address for data collection. Due to tester buss speed limits and inherent internal logic design and tester latency""s, it is impossible to run the array BIST at megahertz and gigahertz clock speeds to detect the AC faults. To do this, the invention uses on chip clock generation (OPCG) with a phase lock loop (PLL) to clock the array BIST at these high speeds. To map the failing array""s with AC faults, the invention uses on chip BIST clock gating that immediately disables the clocks when the BIST compare circuitry detects a fail. The fail is then detected at the external tester pin a few cycles after it occurred. This allows the tester to run and detect fails at its slower speeds. The tester detects the fails and scans the diagnostic register for the failing address and data information. Upon a completion of the fail data collection, the tester asserts the internal BIST clock back on and continues to the next failing address. This inventive method of freezing the internal clocks on fail, preserves the BIST machine status so it can be restarted to the next failing address without restarting the BIST machine for each failing address and also allows for bitmapping at speed. Thus, with the invention, test time is reduced, test coverage is increased, and AC fault diagnosability is gained.
It is, therefore, an object of the present invention to provide a structure and method for an integrated circuit which includes a read/write memory having a plurality of memory devices, (each of the memory devices has a unique address), a built-in self-test (BIST) engine, (the BIST engine has a controller responsive to a test enable signal and operative to generate and store test data in the read/write memory), a comparator operative to compare retrieved data read from the read/write memory and the test data during a single pass test, (the comparator identifying failed cycles where the retrieved data does not correspond correctly to the test data), and a diagnostic unit operative to store the failed cycles and being responsive to the controller regenerating and re-storing the test data in the read/write memory and operative to store failed data and failing addresses, wherein the BIST engine stops only at each of the failed cycles during the single pass test. The BIST engine stops at each of the failed cycles and restarts without reinitailzing during the first pass test and performs only the first pass test. The diagnostic unit uses redundant registers within the integrated circuit which retrieves address and compare data, the read/write algorithm, and the test pattern being run on the failed memory devices when the BIST engine stops at each of the failed cycles.
The invention also comprises a method of operating a built in self test (BIST) engine upon read/write memory within an integrated circuit, including initializing the BIST engine; performing a single pass test on the integrated circuit failed cycles which includes stops at each of the failed cycles; and storing addresses of the failed memory devices during the stops.